Modern integrated circuits are formed on the surfaces of semiconductor substrates, which are mostly silicon substrates. Semiconductor devices are isolated from each other by isolation structures formed at the surfaces of the respective semiconductor substrates. The isolation structures include field oxides and shallow trench isolation (STI) regions.
With the down-scaling of integrated circuits, STI regions are increasingly used as the isolation structures. FIGS. 1 and 2 illustrate intermediate stages in the formation of an STI region. First, as shown in FIG. 1, opening 112 is formed in substrate 110, for example, by etching. Opening 112 has an aspect ratio, which is equal to the ratio of depth D1 to width W1. The aspect ratio becomes increasingly greater when the integrated circuits are scaled down. For 40 nm technology and below, the aspect ratio will be greater, and sometimes far greater, than 7.0. Liner oxide 114 is formed in opening 112. Next, as shown in FIG. 2, oxide 116, preferably a silicon oxide, is filled into opening 112, until the top surface of oxide 116 is higher than the top surface of substrate 110.
The increase in the aspect ratio causes problems. Referring to FIG. 2, in the filling of the opening, the high aspect ratio will adversely result in the formation of void 117, which is a result of the pre-mature sealing in the top region of oxide 116. After a chemical mechanical polish (CMP) to remove excess oxide 116, or after the subsequent cleaning process that lowers the top surface of oxide 116, void 117 may be exposed. In subsequent process steps, conductive materials, such as polysilicon, may be filled into the opening, causing the bridging, and even the shorting, of integrated circuits in some circumstances.
Conventionally, oxide 116 is often filled using one of the two methods, high-density plasma chemical vapor deposition (HDPCVD, also known as HDP) and high aspect-ratio process (HARP). The HDP may fill gaps with aspect ratios less than about 6.0 without causing voids. The HARP may fill gaps with aspect ratios less than about 7.0 without causing voids. However, as the aspect ratios are close to 7.0, even if no voids are formed, the central portion of oxides 116 formed using the HARP is often weak. The weak portions may be damaged by the CMP processes, which in turn cause voids as a result of the CMP. When the aspect ratios further increase to greater than about 7.0, voids start to appear even if the HARP is used. Accordingly, the existing gap-filling techniques can only fill gaps having aspect ratios less than 7.0 without causing voids.
In addition to the above-discussed problem, the conventional gap-filling methods also incur problems in the formation of fin field-effect transistors (FinFETs). For example, FIGS. 3 and 4 illustrate a process for forming semiconductor fins that are used for forming FinFETs. In FIG. 3, after STI regions 120, which include liner oxide 114 and oxide 116, are formed, pad layers and hard masks (not shown) are removed. Next, as shown in FIG. 4, STI regions 120 are recessed so that fins 118 stand above the remaining portions of STI regions 120. However, since STI regions 120 include liner oxide 114 and oxide 116, with liner oxide 114 being denser than oxide 116, in the recessing of STI regions 120, the loose structure of oxide 116 results in rapid downward etching, and hence fences 122 (the residue of STI regions 120) are formed on sidewalls of fins 118. In the subsequent formation of gate dielectrics of the FinFETs (not shown), fences 122 result in the reduction of the amount of oxygen reaching fins 118, and hence the thickness of the resulting gate dielectrics, particularly in regions close to the top surface of the remaining portions of STI regions 120. Further, fences 122 may act as parts of gate dielectrics of the FinFETs. Due to the low quality of fences 122, leakage currents of the resulting FinFETs increase. Experiments have revealed that when the flash memory cells, based on the structure as shown in FIG. 4, are subject to 10,000 writing cycles, the threshold voltages significantly increase, indicating significant leakage currents.